[PATCH RESEND] mtd: nand: allow NAND_NO_SUBPAGE_WRITE to be set from driver

[Scott Wood]

On 08/01/2012 08:05 AM, Matthieu CASTET wrote:
> Hi Scott,
> 
> Scott Wood a écrit :
>> On 07/31/2012 02:33 AM, Matthieu CASTET wrote:
>>> Hi,
>>>
>>> for ONFI flash (like this micron one) the information should be extracted form
>>> the ONFI table (programs_per_page IIRC)
>>>
>>> This should be better than relying on the SOC driver for setting this flags.
>>
>> This is for cases where the constraint is the controller, not the chip.
>>
>>> Does the gpmi driver set this flag because it do not support partial write ?
>>> In this case why it doesn't set  chip->ecc.steps to 1 ?
>>
>> Why is it better to lie about ECC geometry than to just say "subpage
>> writes aren't supported"?  Does/will the ECC geometry get used by upper
>> layers in evaluating the number of corrected bitflips?
> If it is not because of ecc geometry, why the controller doesn't support subpage
> writes ?

I can't answer for GPMI, but in the case of Freescale eLBC/IFC, the
controller only does ECC when you do a full page transaction -- but the
ECC is still done in steps, which is relevant for bitflip thresholds.

-Scott