[PATCH v2 1/2] omap3 nand: cleanup for not to use GPMC virtual address

[Tony Lindgren]

Few more comments below.

* Sukumar Ghorai <s-ghorai at ti.com> [100514 08:18]:
> +
> +/**
> + * gmpc_ecc_init - Initialize the HW ECC for NAND flash in GPMC controller
> + * @cs: Chip select number
> + * @ecc_size: bytes for which ECC will be generated
> + */
> +void gpmc_ecc_init(int cs, int ecc_size)
> +{
> +	unsigned int val = 0x0;
> +
> +	/* Read from ECC Control Register */
> +	val = gpmc_read_reg(GPMC_ECC_CONTROL);
> +
> +	/* Clear all ECC | Enable Reg1 */
> +	val = ((0x00000001<<8) | 0x00000001);
> +	gpmc_write_reg(GPMC_ECC_CONTROL, val);
> +
> +	/* Read from ECC Size Config Register */
> +	val = gpmc_read_reg(GPMC_ECC_SIZE_CONFIG);
> +	/* ECCSIZE1=512 | Select eccResultsize[0-3] */
> +	val = ((((ecc_size >> 1) - 1) << 22) | (0x0000000F));
> +	gpmc_write_reg(GPMC_ECC_SIZE_CONFIG, val);
> +}

There should be some locking as only one chipselect can use
the ECC or prefetch engine at a time. If you have NAND in
two chipselects, bad things would happen..

Maybe something like:

int gpmc_ecc_request(int cs);
void gpmc_ecc_free(int cs);
int gpmc_prefetch_request(int cs);
void gpmc_prefetch_free(int cs);

Other than that, looks like a good clean-up so we can easily
add the platform init code for all the board files.

Regards,

Tony