[PATCH v2] mtd-nand: davinci: correct 4-bit error correction

[Jon Povey]

Sudhakar Rajashekhara wrote:
> On TI's DA830/OMAP-L137, DA850/OMAP-L138 and DM365, after setting the
> 4BITECC_ADD_CALC_START bit in the NAND Flash control register to 1 and
> before waiting for the NAND Flash status register to be equal to 1, 2
> or 3, we have to wait till the ECC HW goes to correction state.
> Without this wait, ECC correction calculations will not be proper.
>
> This has been tested on DA830/OMAP-L137, DA850/OMAP-L138, DM355 and
> DM365 EVMs.
>
> Signed-off-by: Sudhakar Rajashekhara <sudhakar.raj at ti.com>
> Acked-by: Sneha Narnakaje <nsnehaprabha at ti.com>
> Cc: David Woodhouse <dwmw2 at infradead.org>
> Signed-off-by: Andrew Morton <akpm at linux-foundation.org>

Have these people acked and signed off this new version of the patch?

> Since v1:
> a. Timeout has been changed from 100 msec to 100 usec.
> b. Comment above the do, while loop was not matching the code.
>    This has been corrected.
> c. Initialization of 'timeo' variable has been moved down.
> d. It was observed that, while calculating the time in the loop,
>    if there is a context switch between setting the
>    4BITECC_ADD_CALC_START bit and reading of ECC_STATE field, then
>    the loop will not come out until the timeout happens. To prevent
>    the context switch, spin_lock_irqsave and spin_unlock_irqrestore
> are used.

d. means interrupts are disabled for up to 100us while waiting for ECC.
Doesn't sound good if it can be avoided.

How about instead of spinlock, set timeo first time inside the loop?