[PATCH 3/8 v2] mtd: Add MPC5121 NAND Flash Controller driver

[Grant Likely]

On Wed, Jan 27, 2010 at 5:07 AM, Anatolij Gustschin <agust at denx.de> wrote:
> From: Piotr Ziecik <kosmo at semihalf.com>

Again, it is appropriate for you to claim patch ownership now as long
as you preserve the signed-off-by history.

>
> Adds NAND Flash Controller driver for MPC5121 Revision 2.
> All device features, except hardware ECC and power management,
> are supported.

A few comments below.

> diff --git a/arch/powerpc/platforms/512x/mpc512x_shared.c b/arch/powerpc/platforms/512x/mpc512x_shared.c
> index 4745028..6b8314c 100644
> --- a/arch/powerpc/platforms/512x/mpc512x_shared.c
> +++ b/arch/powerpc/platforms/512x/mpc512x_shared.c
> @@ -82,6 +82,7 @@ void __init mpc512x_init_IRQ(void)
>  static struct of_device_id __initdata of_bus_ids[] = {
>        { .compatible = "fsl,mpc5121-immr", },
>        { .compatible = "fsl,mpc5121-localbus", },
> +       { .compatible = "fsl,mpc5121-nfc", },
>        {},
>  };

This hunk shouldn't be in this patch since it touches arch code.  Keep
the NAND and arch bits in separate patches.

Also, this is probably not what you really want.  Doing it this way
means that each of the child nodes also get registered as of_platform
devices.  You want the platform code to only register the nfc at 40000000
node.

> +static int __init mpc5121_nfc_probe(struct of_device *op,
> +                                       const struct of_device_id *match)

__devinit

> +{
> +       struct device_node *rootnode, *dn = op->node;
> +       struct device *dev = &op->dev;
> +       struct mpc5121_nfc_prv *prv;
> +       struct resource res;
> +       struct mtd_info *mtd;
> +#ifdef CONFIG_MTD_PARTITIONS
> +       struct mtd_partition *parts;
> +#endif
> +       struct nand_chip *chip;
> +       unsigned long regs_paddr, regs_size;
> +       const uint *chips_no;
> +       int resettime = 0;
> +       int retval = 0;
> +       int rev, len;
> +
> +       /*
> +        * Check SoC revision. This driver supports only NFC
> +        * in MPC5121 revision 2.
> +        */
> +       rev = (mfspr(SPRN_SVR) >> 4) & 0xF;
> +       if (rev != 2) {
> +               dev_err(dev, "SoC revision %u is not supported!\n", rev);
> +               return -ENXIO;
> +       }

*Only* revision 2?  Are future revisions of silicon assumed to be broken then?

> +static int __exit mpc5121_nfc_remove(struct of_device *op)

__devexit

> +static struct of_device_id mpc5121_nfc_match[] = {

...match[] __devinitdata = {

> +       { .compatible = "fsl,mpc5121-nfc", },
> +       {},
> +};
> +
> +static struct of_platform_driver mpc5121_nfc_driver = {
> +       .match_table    = mpc5121_nfc_match,
> +       .probe          = mpc5121_nfc_probe,
> +       .remove         = __exit_p(mpc5121_nfc_remove),

__devexit_p()

g.

-- 
Grant Likely, B.Sc., P.Eng.
Secret Lab Technologies Ltd.