[PATCH v2 2/6]nand/denali: Add bad block management for MRST

[Dong, Chuanxiao]

> (Actually, we *can* -- you don't use these options anywhere (yet?)
> except as a gateway to letting us set the BBT_BLOCKNUM value.
> 
> It may also be worth switching CE4100 to use the same BBT scheme as
> you're using in MRST -- don't all the same arguments apply there?
> 
> I'm guessing that you didn't change CE4100 just because you want to
> retain on-medium compatibility? Let's ask Jason -- I suspect it would be
> OK to change...
[Chuanxiao Dong] It will be better if CE4100 can use this BBT. But from the
original denali.c, I found CE4100 maybe don't have a protected partition like
MRST does. In MRST, its IAFW is stored in this partition. This partition is
created by SCU FW. So MTD driver doesn't have any permission to access this
partition. So the BBT can't be created by scanning NAND from the beginning.
It need to skip the protected partition. Here is the biggest difference between
MRST and CE4100. This is just I got from code..... Never confirmed with DHG guys.


> I'm also somewhat dubious about the way we abandon the BBT when we're
> going to use Spectra -- and especially the use of the scratch register.
> Can't we put that information into PCI config space if we really must
> have it? I'll look over that in more detail...
[Chuanxiao Dong] Spectra + MTD only used in two ways.
1) Spectra only manage a few blocks as well as IAFW. In this way, means Spectra
is used to update Kernel or something like bootloader. No file system allowed.
In this way, BBT will not contain these blocks information.
2) Spectra manage the whole NAND as well as IAFW. That means no NAND file
system allowed. Only EXT3 will be used. So in this way, MTD driver doesn't create BBT.

So I think, BBT will have no influence to Spectra.
Scratch register just used to let MTD driver know how many blocks IAFW managing. So
what will be the effect of using scratch register?