Advice on New Hardware Platform

[Jim Duda]

I have designed a new NAND Flash Controller which supports ECC at the hardware layer.
It can be programmed to support between 6-30 bits of Reed Solomon correction over 512 or 1024K bytes of data.
The controller supports the following four main functions in hardware:

1.CLE cycles of 1 to 15 bytes of information
2. ALE cycles of 1 to 15 bytes of information
3. Page Write with DMA calculating ECC on the fly
4. Page Read with DMA correcting bytes using ECC on the fly.

ECC is stored intermixed with data, using main and spare data as one piece.
The combination of the four main functions can be used to support most devices.
I'm now investigating how to map this design to the MTD layer.

I've read all of the documentation I can find.
Since my new hardware does ECC on the fly, I'm struggling to determine which "model" to use.

Can anyone suggest an example driver to use as a starting point?

Any advice appreciated.

Thanks,

Jim