[PATCH 2.6.30-rc6 3/3] NAND: Add 4-bit ECC support for large page NAND chips
Narnakaje, Snehaprabha
nsnehaprabha at ti.com
Fri May 22 23:51:52 EDT 2009
Hi,
I will be coming up with an updated patch for this (3/3) early next week to address -
1. Corrections to eccpos[]
2. Comments from Troy
Thanks
Sneha
> -----Original Message-----
> From: David Brownell [mailto:david-b at pacbell.net]
> Sent: Wednesday, May 20, 2009 8:38 PM
> To: davinci-linux-open-source at linux.davincidsp.com; Narnakaje, Snehaprabha
> Cc: linux-mtd at lists.infradead.org; dwmw2 at infradead.org;
> tglx at linutronix.de; akpm at linux-foundation.org
> Subject: Re: [PATCH 2.6.30-rc6 3/3] NAND: Add 4-bit ECC support for large
> page NAND chips
>
> Minor comment: $SUBJECT should say it adds this "for DaVinci". ;)
>
> To recap other discussion (I hope), this needs to be reissued since:
>
> On Monday 18 May 2009, nsnehaprabha at ti.com wrote:
> > +static struct nand_ecclayout hwecc4_2048 __initconst = {
> > + .eccbytes = 40,
> > + .eccpos = { 0, 1, 2, 3, 4,
>
> Byte 0 -- for 8-bit large-page parts which need this patch -- is
> the manufacturer bad block marker, and the idea was to *not* clobber
> it. Those bytes need to be skipped.
>
> Will the 40 bytes of ECC data now be stored at offsets 24..63,
> matching Troy's patches?
>
> 0..1 manufacturer badblock markers
> 8..11 BBT marker ("free" oob data)
> 16..23 JFFS2 stuff ("free" oob data)
> 24..63 ECC data
>
> And for 4KB pages, it would be the same -- except that
> there would be 80 bytes of ECC data, from 48..127 (too
> much to fit into the eccpos array).
>
>
> > + /* offset 5 holds the badblock marker */
> > + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
> > + /* 8 bytes at offset 16 hold JFFS2 clean markers */
> > + 24, 25, 26, 27, 28,
> > + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38,
> > + 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, },
> > + .oobfree = {
> > + {.offset = 16, .length = 8, },
> > + {.offset = 49, },
> > + },
> > +};
>
>
More information about the linux-mtd
mailing list