[PATCH 3/5] mtd: nand: atmel: use default ecc layout

[Troy Kisky]

Richard Genoud wrote:
> 2009/5/15 Richard Genoud <richard.genoud at gmail.com>:
>> 2009/5/14 Troy Kisky <troy.kisky at boundarydevices.com>:
>>> Haavard Skinnemoen wrote:
>>>> I also suspect it will break hardware ECC. The ECC controller is a bit
>>>> picky about the OOB layout, which is why the defaults were overriden in
>>>> the first place.
>>>>
>>>> Haavard
> 
> Looking at the first 2 patches on nand_base.c, it seems that the HW
> ECC layout for small pages will be the same (ecc at offsets 0,1,2,3)
> wich is good (because it's the only possible place).
> 
> For large pages, the HW ECC layout will change from [60,61,62,63] to
> [2,3,4,5]. The ecc will still be correct, but as david said, the
> compatibility won't.
> 
> richard.

I think you are wrong. It is definitely not what I intended.
The logic should say, "If I can place the ecc at the beginning I will,
otherwise, I will place it at the end." With the bad block marker
at 0, it should choose the end.


Troy