[PATCH 2/2] NAND on DM355: Add 4-bit ECC support for large page NAND chips

[vimal singh]

On Thu, May 7, 2009 at 10:24 PM, David Brownell <david-b at pacbell.net> wrote:
> On Thursday 07 May 2009, vimal singh wrote:
>> >> How about leaving bytes '4' and '5' for bad block marker, to support 16-bit
>> >> NAND parts too.
>> >
>> > This 4-bit ECC engine only works for 8-bit wide parts ...
>> > or are you suggesting that in case TI re-engineers that
>> > engine in the future?
>>
>> I am omap guy and was not aware of that. In omap HW BCH
>> ECC (4- or 8- bit correction)can work both kind of memories.
>
> I'm somewhat more of an OMAP guy too -- just got sucked in to
> trying to get a dm355 board to run off NAND in mainline-bound
> code, and you can see where that landed me!
>
> Last I looked at the OMAP2/OMAP3 NAND controller driver, it
> didn't yet support most fancy hardware features, like ECC
> using more than one bit or the prefetch/postwrite logic.
I planned to push simple driver first, as it is present in L-O tree,
and then pushing other features later.
'prefetch-read/post-write' logic has been already implemented
in omapkernel git (For which sometime back I submitted patch on L-O list).
I'll be pushing those patches separately.

ECC using more than one bit (i.e. 4- or -8 bit) can be implemented
by configuring HW ECC engine accordingly in BCH ECC mode. But this
feature is still not implemented, may be in future I'll be
looking into this.

---
Regards,
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