[PATCH 2/2] NAND on DM355: Add 4-bit ECC support for large page NAND chips

[vimal singh]

On Thu, May 7, 2009 at 2:41 PM, David Brownell <david-b at pacbell.net> wrote:
> On Thursday 07 May 2009, vimal singh wrote:
>> > Comments would be good, highlighting (a) byte 5 is reserved,
>> > it's the manufacturer bad block marker, (b) 8 bytes @16 are
>> > expected by JFFS2.  Not everyone will "just know" those.
>>
>> How about leaving bytes '4' and '5' for bad block marker, to support 16-bit
>> NAND parts too.
>
> This 4-bit ECC engine only works for 8-bit wide parts ...
> or are you suggesting that in case TI re-engineers that
> engine in the future?
I am omap guy and was not aware of that. In omap HW BCH ECC (4- or 8- bit
correction)can work both kind of memories.

Regards,
vimal