[PATCH v3 3/4] powerpc: NAND: FSL UPM: document new bindings
wg at grandegger.com
Thu Mar 26 18:14:42 EDT 2009
Anton Vorontsov wrote:
> On Thu, Mar 26, 2009 at 11:02:06AM -0600, Grant Likely wrote:
>>>> Here is another thought. The binding is describing that address lines
>>>> are used to activate CS lines. Offset for chip access purposes is
>>>> derived from the address line, but it doesn't directly describe the
>>>> hardware. The following may be a better description of the hardware.
>>>> fsl,upm-addr-line-cs = <9 10>;
>>> The TQM8548 hardware has some logic connected to the two address lines
>>> allowing to select up to 4 chips with two address lines:
>>> fsl,upm-addr-line-cs-offsets = <0x0 0x200 0x400 0x600>
>> Ah. I see. This is board specific then. I think it is premature to
>> try and define a generic solution here because it depends on custom
>> board hardware and different boards could use very different logic.
>> The next board could end up doing something completely different. I'd
>> rather start to see trends in multiple boards implementing the same
>> scheme before trying to craft a generic scheme.
>> In other words, this device is not register-level compatible with the
>> fsl,upm-nand device. Give the node a new compatible value
>> (tqc,tqm8548-upm-nand) and add another entry to the of_fun_match table
>> for the new device. Use the .data element in the match table to
>> supply an alternate fun_cmd_ctrl() function for this board (instead of
>> using a property value do decide which fun_cmd_ctrl() behaviour to
>> use). New boards that *do* use the same addressing scheme can claim
>> compatibility with tqc,tqm8548-upm-nand.
> I don't like this. :-/
> UPM is an universal thing, so there are thousands of ways we can
> connect NAND to the UPM. Of which only ~10 would be sane (others are
> insane, and nobody would do this. If they do, _then_ we'll fall back
> to <board>-upm-nand scheme for a particular board).
> I don't see any problem with fsl,upm-addr-line-cs-offsets. It can
> describe any scheme in "addr lines are cs" connection, it's a common
> setup for multi-chip memory, we shouldn't treat it is as something
I fully agree. I'm going to provide a patch on monday.
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