query: nand read/write method for 2048 + 64 byte page

[vimal singh]

I am implementing BCH HW ECC method (present in omap2/3), which can
provide ECC protection
for spare area bytes too, along with main area bytes.
Below are few details:
1. It is a large page NAND device
2. We are looking for upto 4-bit error correction (for each 512 + 9 bytes)

Nand has 2048 + 64 bytes page size. (main area + spare area). The
layout I am creating is:
(all other possible layouts are similar to this only for this HW ECC scheme)

|<------main area, divided into 4-sectors----->|<-----Protected spare
area------>|<----------ECC bytes-------->|
|   512      +    512    +    512    +    512      |    9    +    9
+    9    +    9    |   7   +   7   +   7   +   7    |
|<-- 1st --> <-- 2nd --> <-- 3rd --> <-- 4th -->|<-1st-> <-2nd->
<-3rd-> <-4th->|<1st> <2nd> <3rd> <4th>|

i.e. 7 ECC bytes (52 bits in actual) for each 512 + 9 bytes (main +
spare), to correct up to 4- errors.


My concern is that, none of the present ECC scheme (in nand_base.c)
seems suitable for this.
Do I need to implement new ECC scheme, and hence new read / write API's?

In that case too, main question is: how to handle oob read/write for
such layout? (where spare
area bytes are protected along with main are ECC)

Any suggestion / help is appreciated.
Thanks in advance.

---
Regards,
Vimal