UBIFS Corrupt during power failure
dedekind at infradead.org
Thu Jul 16 03:09:59 EDT 2009
On Wed, 2009-07-15 at 21:52 +0100, Jamie Lokier wrote:
> I suspect that's quite common for NOR cells.
> Here's a question: Does it ever happen for NAND cells? Does the UBIFS
> code assume that NAND erase only _ever_ converts 0 bits to 1 bits,
> never 1 bits to 0 bits temporarily?
I'm not good in physics of those processes, but AFAIU during the erasure
all bits are set from 0 to 1 on NAND, and this is a simultaneous process
for all bits in the eraseblocks. But I cannot say for sure.
> Can the same problem arise with NAND? I don't mean "every NAND we
> tested", but NAND in general? Is it correct to assume they never
> convert 1 bits to 0 bits temporarily during the erase cycle, and
> should the UBIFS code write something to the PEB which invalidates the
> header to ensure this cannot result in the same problems we've seen
> with NOR?
Good question, but I cannot tell for all NANDs, unfortunately. But the
one we tested is fine :-) But yes, would be nice to hear a HW expert.
> You can't necessarily overwrite the header with NAND, but you might be
> able to write elsewhere to say "this PEB is undergoing erase and is
> therefore indeterminate".
Yes, we may write to OOB, after all.
Artem Bityutskiy (Битюцкий Артём)
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