UBIFS Corrupt during power failure
Eric_Holmberg at Trimble.com
Wed Jul 15 17:36:47 EDT 2009
> Artem Bityutskiy wrote:
> > So it indeed looks like NOR erasure includes writing zeroes from the
> > end. Unfortunately UBI/UBIFS cannot handle this correctly ATM.
> For that chip. I wouldn't like to assume all NOR chips use the same
> erase algorithm.
> Also, remember that little problem with the 8-byte write buffer?
Yes, the configurable buffer size is still a to-do item.
> I guess it's possible that it's pre-erase-to-zero step might write
> zeros in 8-byte blocks too, or in some other size depending on how the
> hardware works. And when it erases bytes in parallel, there's no
> guarantee about the order you'll see the bits change if it's
> interrupted by a power cycle.
> So I guess the right thing is to assume nothing, just that the whole
> block may have bits flipped from 1 to 0 in an indeterminate order, and
> then all bits flipped from 0 to 1 in an indeterminate order.
> Or maybe the weaker assumption, that the whole block is indeterminate
> during erase.
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