Help requested with Eureka EP501 NAND flash controller.

[Darren B. Hutchinson]

Hi All,

I'm looking to interface a device containing the Eureka EP501 NAND flash controller ( http://www.eurekatech.com/products/memory/ep501.htm )

I've looked through the last twelve months of archives. I found lot of answers to questions I'll get to later, but no mention of the Eureka controller.

So first question - has anybody ported for the EP501 and can they share it?

Unless I'm the luckiest person on earth I guess I still have a driver to write. I've looked through the code & documentation for a few days and I think I know how to write a suitable driver based on the existing NAND code - but I'd really appreciate any knowledgeable opinions you could share.

The EP501 is fairly, well, controlling. It wants to generate and write the ECC/BCH by itself at the end of write and read operation. It also wants to issue the commands to the flash itself and often routes the data to/from registers it keeps for specific purposes. There is no direct access to the NAND flash control signals (CLE/ALE/etc)

For example if you tell it to read the device ID the data goes to special registers on the device and must be read from there. Page data goes to a different set of access register.

Based on my examination of the code it looks like the right approach would be:

- set ecc.type to NAND_ECC_HW_SYNDROME

- provide functions for ecc.correct()/ecc.calculate()/ecc.read_page()/ecc.write_page()/ecc.read_oob()/ecc.write_oob() to access the page via the EP501 using its ECC/BCH engines

- provide chip.cmd_ctrl() to catch the flash commands and forward them to the EP501

- provide chip.read_byte()/chip.write_byte() to fetch non-page access commands (ie read device ID) from the command-dependent register on the EP501

Does this sound right? Is there a better way to solve the problem?

Thanks in advance for any guidance you can give,

Darren Hutchinson (Ikanos Communications)