[patch 3/3] mtd-nand: DaVinci: Add 4-bit ECC support for large page NAND chips

[Narnakaje, Snehaprabha]

Troy,

> -----Original Message-----
> From: Troy Kisky [mailto:troy.kisky at boundarydevices.com]
> Sent: Friday, August 07, 2009 3:54 PM
> To: akpm at linux-foundation.org
> Cc: dwmw2 at infradead.org; linux-mtd at lists.infradead.org; Narnakaje,
> Snehaprabha; dbrownell at users.sourceforge.net; Paulraj, Sandeep;
> tglx at linutronix.de
> Subject: Re: [patch 3/3] mtd-nand: DaVinci: Add 4-bit ECC support for
> large page NAND chips
> 
> akpm at linux-foundation.org wrote:
> > From: Sneha Narnakaje <nsnehaprabha at ti.com>
> >
> > This patch adds 4-bit ECC support for large page NAND chips using the
> new
> > ECC mode NAND_ECC_HW_OOB_FIRST.  The platform data from board-dm355-evm
> > has been adjusted to use this mode.
> >
> > The patches have been verified on DM355 device with 2K Micron devices
> > using mtd-tests and JFFS2.  Error correction upto 4-bits has also been
> > verified using nandwrite/nanddump utilities.
> >
> > Reviewed-by: David Brownell <dbrownell at users.sourceforge.net>
> > Signed-off-by: Sneha Narnakaje <nsnehaprabha at ti.com>
> > Signed-off-by: Sandeep Paulraj <s-paulraj at ti.com>
> > Cc: David Woodhouse <dwmw2 at infradead.org>
> > Cc: Thomas Gleixner <tglx at linutronix.de>
> > Signed-off-by: Andrew Morton <akpm at linux-foundation.org>
> > ---
> >
> >  drivers/mtd/nand/davinci_nand.c |   45 ++++++++++++++++++++++++++----
> >  1 file changed, 39 insertions(+), 6 deletions(-)
> >
> > diff -puN drivers/mtd/nand/davinci_nand.c~mtd-nand-davinci-add-4-bit-
> ecc-support-for-large-page-nand-chips drivers/mtd/nand/davinci_nand.c
> > --- a/drivers/mtd/nand/davinci_nand.c~mtd-nand-davinci-add-4-bit-ecc-
> support-for-large-page-nand-chips
> > +++ a/drivers/mtd/nand/davinci_nand.c
> > @@ -348,6 +348,12 @@ compare:
> >  	if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
> >  		return 0;
> >
> > +	/*
> > +	 * Clear any previous address calculation by doing a dummy read of
> an
> > +	 * error address register.
> > +	 */
> > +	davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
> > +
> >  	/* Start address calculation, and wait for it to complete.
> >  	 * We _could_ start reading more data while this is working,
> >  	 * to speed up the overall page read.
> > @@ -359,8 +365,10 @@ compare:
> >
> >  		switch ((fsr >> 8) & 0x0f) {
> >  		case 0:		/* no error, should not happen */
> > +			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
> >  			return 0;
> >  		case 1:		/* five or more errors detected */
> > +			davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
> >  			return -EIO;
> >  		case 2:		/* error addresses computed */
> >  		case 3:
> > @@ -500,6 +508,26 @@ static struct nand_ecclayout hwecc4_smal
> >  	},
> >  };
> >
> > +/* An ECC layout for using 4-bit ECC with large-page (2048bytes) flash,
> > + * storing ten ECC bytes plus the manufacturer's bad block marker byte,
> > + * and not overlapping the default BBT markers.
> > + */
> > +static struct nand_ecclayout hwecc4_2048 __initconst = {
> > +	.eccbytes = 40,
> > +	.eccpos = {
> > +		/* at the end of spare sector */
> > +		24, 25, 26, 27, 28, 29,	30, 31, 32, 33,
> > +		34, 35, 36, 37, 38, 39,	40, 41, 42, 43,
> > +		44, 45, 46, 47, 48, 49, 50, 51, 52, 53,
> > +		54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
> > +		},
> > +	.oobfree = {
> > +		/* 1 byte at offset 0 holds manufacturer badblock marker */
> > +		{.offset = 1, .length = 23, },
> 
> I thought Sneha Narnakaje was going to change offset = 2, length = 22 ?

Troy,

Sorry, may be I didn't understand. I thought the suggestion was to change the offset in nand_bbt.c.

I will resubmit this patch, with the suggested change.

Thanks
Sneha

> 
>