UBIFS Corrupt during power failure

[Eric Holmberg]

> -----Original Message-----
> From: Jamie Lokier [mailto:jamie at shareable.org] 
> Sent: Wednesday, April 15, 2009 12:38 PM
> To: Nicolas Pitre
> Cc: Eric Holmberg; Urs Muff; linux-mtd at lists.infradead.org; 
> Adrian Hunter
> Subject: Re: UBIFS Corrupt during power failure
> 
> Nicolas Pitre wrote:
> > On Wed, 15 Apr 2009, Jamie Lokier wrote:
> > 
> > > Unrelated to this chip: I vaguely remember, aren't there 
> some flash
> > > chips which can do more than one block write in parallel, 
> or a write
> > > in parallel with an erase to a different block?
> > 
> > Some NOR flash parts can do a write _or_ an erase in one 
> block while 
> > performing any amount of reads in other blocks.  At least 
> that's what we 
> > support.  If some parts allow for concurrent writes we 
> currently don't 
> > support that.
> 
> I don't remember if it was NOR, NAND or something else, but I remember
> reading about some flash which supports 1 concurrent write and 1
> erase, and thinking "oh that's clever, it means you can do streaming
> writes or rapid fsync/database commits without long pauses 
> for erasing".

The evolution seems to be:
 1. Allow erase / program suspend to do a read from a different PEB (the
chip I'm using supports this)
 2. Allow simultaneous read while either erasing or programming a
different PEB
 3. Allow parallel operations on different flash banks
 4. Combine NOR and NAND onto the same chip

My understanding is that the parallel operations are only valid on
different flash banks, where a flash bank could be thought of
conceptually as a separate flash chip.  I'm no flash memory expert by
any means, so I'm sure there are some other systems out there.

> 
> Of course you can do that with two flash chips side by side :-)
> 
> Can MTD and/or UBI join two chips to look like a single partition in
> that way and avoid pauses for erase by writing to the other part?

The CONFIG_MTD_CONCAT option will join multiple chips together into a
single MTD device, but I haven't looked into the code to see if it
allows simultaneous operations on the separate chips.

Nothing like RAID0 on flash :)

-Eric