Run UBIFS on top of IDE mode NAND disk?

[Jamie Lokier]

Artem Bityutskiy wrote:
> Hi,
> 
> On Tue, 2009-04-14 at 23:10 -0700, Subodh Nijsure wrote: 
> > I have board with 4GB NAND memory chip, it is configured to
> > operate in IDE mode. And currently I am creating ext3 file-system
> > on it.  This chip also have on-board controller that does
> > wear-levelling, ECC so the quesitons are:
> >  
> > Can I (Should I) run UBIFS on of it and gain more of wear-levelling or its
> > not worth it? 
> 
> Vs "Can I": if this is raw NAND, you just need an MTD driver for it.
> Then you can use UBI/UBIFS on top of that.
> 
> Vs "Should I": you really should not ask questions like this. It is a
> question of your design. Look at your NAND and how many erase cycles
> each eraseblock survives. Then roughly calculate how many years or
> months it should survive with ext3, which has fixed-position journal
> and inode table and bitmap. Then decide whether you need WL or not.
> Everything depends on your requirements.
> 
> Also, if this is raw NAND, then HW does not hide bad blocks for you,
> right? How will you manage bad eraseblocks then, ext3 cannot do this.
> It just panics in case of any I/O error.

But the on board controller does wear-levelling, he said.

I think the question is whether the on board controller's
wear-levelling is good or not.  If it's low quality, UBI will do it
better.  If the controller is good quality, there's no need for UBI on
top of it.

I guess that two layers of good quality wear levelling just adds more
wear, because they both copy data around.

If it can be used as raw NAND, and the chip really is a NAND with
standard NAND properties, _and_ if it's possible to disable the
controller's wear levelling and get direct NAND access, then at least
you know that UBI provides a good quality wear levelling
implementation, and you have access to some statistics too.

-- Jamie