Question on how NAND flash BBT is stored in the chip

[Rutger Hofman]

Good afternoon list,

I have a question how the BBT (bad block table) is stored in MTD NAND 
devices. I googled for a while, and browsed the code, but I am still not 
sure.

The question:
Is the BBT stored/retrieved using a spare layout? Is ECC 
generation/correction done for it?

This question derives from the question above: is the BBT marker pattern 
stored within a spare layout (with slots for ECC, bad block markers 
etc)? Or is it written verbatim (raw and unmangled) into the spare area?

If no ECC is used for the BBT, is that for a reason?

Thanks for the information,

Rutger Hofman
VU Amsterdam