bus access for NAND parts
matthieu.castet at parrot.com
Tue Nov 4 05:11:23 EST 2008
Ricard Wanderlof a écrit :
> On Thu, 30 Oct 2008, Cliff Brake wrote:
>> Correction -- above should say: "It seems that most devices simply use a
>> _GPIO_ for CE". The chip select is set low in software, and then
>> multiple bus cycles are run to execute the address and data phases of
>> the NAND operation. So what keeps another process from interrupting
>> this and running a bus cycle while the GPIO for NAND CE is still low
>> -- which would toggle the strobes to the NAND cs.
> I don't know in general, but in several systems that have multiple buses,
> the NAND flash can be the only device on a particular bus, so conflicts
> with other devices are not an issue in those cases. Otherwise, it would be
> as you say, I agree.
The s3c2412 where the nand bus is shared with SDRAM. nCE is like a gpio
set by software. But it isn't a problem because the nand flash doesn't
care about other bus cycle if nWE/nRE is in high state (see nand
So the arbitration is done with nWE/nRE line and without nCE.
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