Problem with Micron 256 MB NAND on 440EPx

[Andrew E. Mileski]

Alessandro Rubini wrote:
>> I've now verified with a logic analyzer that the NFREN strobe is active 
>> during when NFRDYBSY is low (NAND chip is busy), and latching bogus data 
>> as a result (the bus has pull-ups so 0xff).
> 
> I had a similar problem with the NDFC on an old kernel. I finally
> tracked it down to a missing mb() (i.e. eieio on the ppc).  The
> problem was triggered by DMA activity on the bus, but could also be
> exposed by lowering NDFC speed.  The hw controller would thus check
> the R/B* pin before the command reached the nand device, so it was not
> busy (yet).  Since I was working with an old kernel and always tight
> of time, I didn't check if the problem was still present in modern
> code.

I hadn't considered a sequencing problem.  I'll give your patch a try 
too.  Thanks!

I went back and noticed that tWB is hardcoded everywhere to 100ns (no 
define or config variable? *sigh*).  My chip can require up to 150ns.  I 
also increased a few other delays.  Those changes, plus the timeout 
calculation bug I posted on in another thread, and adding timeout 
expired warnings (previously silent errors), and it seems to be working 
at the moment.

I'll roll up a patch of it all when I'm satisfied with it after more 
testing.

-- 
Andrew E. Mileski