Bug in nand_base.c , in handling of K9F1208U0B ?

Manu Rao MRao at AlienTechnology.com
Thu May 22 16:30:52 EDT 2008

Hi All, 
I have an Atmel AT91SAM9260 processor interfaced to a K9F1208U0B (
Samsung 64Mbytes Small Block flash device).

The code in nand_base.c and at91_nand.c leads me to believe that the
flash is getting enabled once and then does not get disabled at all( My
scope traces confirm that the CE never goes high) . This seems like it
would work with a CE don't care flash.

However, in the datasheet of the K9F1208U0B( page 31) , it is explicitly
mentioned that the CE has to be driven HIGH at the end of a block read
for greater than 100ns.

Do all flashes that support sequential row read have a requirement that
the CE line should be taken high and then brought low? If yes, then the
current implementation in kernel would violate the requirement.

What implications would this have, if any? I have a situation where I
occasionally get corrupt data from the flash - can this be the cause?
Manu Rao

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