Jffs2 and big file = very slow jffs2_garbage_collect_pass

Ricard Wanderlof ricard.wanderlof at axis.com
Wed Jan 23 09:25:03 EST 2008


On Wed, 23 Jan 2008, Jörn Engel wrote:

>> The only input I have got from chip manufacturers regarding this issue is
>> that with inreasing bit densities and decreasing bit cell sizes in the
>> future, things like the probability of random bit flips are likely to
>> increase. (Somewhere there is a limit when the amount of error correction
>> needed to handle this things grows too large to make the chip practically
>> useful; say 10 error correction bits per stored bit or whatever).
>
> If error rates increase, device drivers have to do stronger error
> correction.  Quality after error correction has been done should stay
> roughly the same.

Yes, true, the first step is to increase the error correction capabilites, 
but there comes a point when there are so many error correction bits 
required per data bit that there is no point of increasing the memory 
size.

Today we have 3 ECC bytes per 256 data bytes in an ordinary nand flash. If 
geometries decrease we might at some point need, say 128 ECC bytes, and 
further down the line perhaps even more ECC bytes than data bytes. It then 
eventually comes to a point of diminishing returns; if the geometries are 
decreased and error rates go up, the increase in number ECC bits might be 
more than the gain in number of data bits. This is far down the line, and 
partly speculative I agree.

/Ricard
--
Ricard Wolf Wanderlöf                           ricardw(at)axis.com
Axis Communications AB, Lund, Sweden            www.axis.com
Phone +46 46 272 2016                           Fax +46 46 13 61 30



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