[PATCH] [MTD] [NAND] nand_base.c: Allowing core driver to choose ECC block size for SW ECC scheme.

[vimal singh]

This patch allows core driver to choose ECC block size in sw ecc case.

Signed-off-by: Vimal Singh <vimalsingh at ti.com>
---
Current nand driver supports 256 and 512 byte software ecc.
This patch provides driver the flexibility to choose ecc size.
'256' bytes will be used by default if not provided by core driver.

--- a/drivers/mtd/nand/nand_base.c	2008-12-12 14:26:30.050002000 +0530
+++ b/drivers/mtd/nand/nand_base.c	2008-12-12 14:27:05.330000000 +0530
@@ -2622,7 +2622,8 @@ int nand_scan_tail(struct mtd_info *mtd)
 		chip->ecc.write_page = nand_write_page_swecc;
 		chip->ecc.read_oob = nand_read_oob_std;
 		chip->ecc.write_oob = nand_write_oob_std;
-		chip->ecc.size = 256;
+		if (!chip->ecc.size)
+			chip->ecc.size = 256;
 		chip->ecc.bytes = 3;
 		break;