[PATCH] [NAND] This patch add support for HW ECC (HSIAO code) on AT91SAM9G20.

[Hong Xu]

Hi Marc,

On Fri, Aug 22, 2008 at 17:47, Marc Pignat <marc.pignat at hevs.ch> wrote:
> Hi all!
>
> On Friday 22 August 2008, Hong Xu wrote:
>> >From ce6b68cf009a94ab12a31d7f007003173b6cad2c Mon Sep 17 00:00:00 2001
>> From: Hong Xu <hong.xu at atmel.com>
>> Date: Fri, 22 Aug 2008 10:29:10 +0800
>> Subject: [PATCH] This patch add support for HW ECC on AT91SAM9G20.
>>
>> AT91SAM9G20 ECC controller is capable of 1-bits error correction
>> and 2-bit random detection for every 256 bytes of data. And this
>> patch chooses a working mode which can be compatible with software
>> ECC.
>
> ...
>
>>
>> +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW_HSIAO
>> +static struct nand_ecclayout nand_oob_16 = {
>> +     .eccbytes = 6,
>> +     .eccpos = {0, 1, 2, 3, 6, 7},
>> +     .oobfree = {
>> +             {.offset = 8,
>> +              . length = 8} }
>> +};
>
> static const?

To be strictly speaking, it's a static const. :-)

>
>> +
>> +static struct nand_ecclayout nand_oob_64 = {
>> +     .eccbytes = 24,
>> +     .eccpos = {
>> +                40, 41, 42, 43, 44, 45, 46, 47,
>> +                48, 49, 50, 51, 52, 53, 54, 55,
>> +                56, 57, 58, 59, 60, 61, 62, 63 },
>> +     .oobfree = {
>> +             {.offset = 2,
>> +              .length = 38} }
>> +};
>> +> ...
>
>> diff --git a/drivers/mtd/nand/atmel_nand_ecc.h
>> b/drivers/mtd/nand/atmel_nand_ecc.h
>> index 1ee7f99..41e072e 100644
>> --- a/drivers/mtd/nand/atmel_nand_ecc.h
>> +++ b/drivers/mtd/nand/atmel_nand_ecc.h
>> @@ -26,6 +26,30 @@
>>  #define              ATMEL_ECC_ECCERR                (1 << 1)                /* ECC Single Bit Error */
>>  #define              ATMEL_ECC_MULERR                (1 << 2)                /* Multiple Errors */
>>
>> +#ifdef CONFIG_MTD_NAND_ATMEL_ECC_HW_HSIAO
>> +
>> +#define ATMEL_ECC_PER_256    (1 << 4)
>> +
>> +#define ATMEL_ECC_PR10               0x38
>> +#define ATMEL_ECC_PR11               0x3c
>> +#define ATMEL_ECC_PR12               0x40
>> +#define ATMEL_ECC_PR13               0x44
>> +#define ATMEL_ECC_PR14               0x48
>> +#define ATMEL_ECC_PR15               0x4c
>> +
>> +#else
>> +
>>  #define ATMEL_ECC_PR         0x0c                    /* Parity register */
>
> Never used, perhaps a future use?

No, it's used. For some AVR chips and At91SAM926x chips, 2 bytes of 4
ECC parity data are read from it.

>
> ...
>>  #endif
>
> Best regards
>
> Marc
>
>
>