BBT structure for NAND flash

[Meher]

HI,
      We have an ARM-9 based board with NAND flash. The ROM boot
laoder will load the kernel loader from NAND and the kernel loader
will load the kernel and pass the file system information to the
kernel. To have a good bad block management scheme for the boot loader
I am planning to use the BBT table generated using MTD API.
   I would like to understand what will be the structure of the BBT
table created using MTD layer? When I set the parameters to created
user defined BBT table say at the end of the flash will the NAND
driver in linux kernel actually create the BBT at the last two blocks
of the physcial NAND block? Can I have my ROM bootlaoder read this BBT
so that it can identify any non-factory bad blocks that arised due to
upgrading of kernel loader.



-- 
Regards,
Meher