Does mtd support two-plane page program for nand flash?

Jörn Engel joern at
Wed Mar 7 09:34:14 EST 2007

On Wed, 7 March 2007 14:57:02 +0800, falls huang wrote:
>     AFAIK , the samsung's nand flash K9LAG08U0M/K9HBG08U1M/K9MCG08U5M
> support two-plane page program. For example: The K9LAG08U0M is
> arranged in four 4Gb memory planes.Each plane contains 2,048 blocks
> and 2112 byte page registers. This allows it to perform simultaneous
> page program and block erase by selecting one page or block from each
> plane. ( refer to the datasheet of K9LAG08U0M)

Interesting.  I was wondering when devices like this would show up.
Do you have a spec for those chips?

>   I have searched the source of mtd/jffs2/jffs3 and I found that them
> don't support two-plane page program . How should I add two-plane page
> program ? Should I modify the source of mtd or jffs2/jffs3 ?

Not sure how much interest in this exists for JFFS2.  Two NOR chips can
work in parallel just as easily as your two-plane chip.  But noone has
ever tried to use this in any way.

For LogFS I am very interested.  Supporting parallel writes to several
chips (or planes on one chip) is on my list.  MTD should export roughly:
 - one device for all planes/chips,
 - preferrably eraseblock interleaving between all planes/chips or
 - alternatively linearly appending all planes/chips,
 - information about how many planes/chips exists.

What is the latency of reads/writes/erases?  I have already asked for
the spec, haven't I? ;)


The cost of changing business rules is much more expensive for software
than for a secretaty.
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