Chip_ready for SST39VF640xB flash

[Niels Gram Jeppesen]

Hi,

I am trying to get the chip_ready function in cfi_cmdset_0002.c to work with the SST39VF640xB flash. What I see is that the current chip_ready report that the chip is ready before it is ready during block erase. Last week I thought that I had fixed the problem but it turned out that the fix did not reliably solve the problem. I have modified chip_ready to gain more knowledge about what is going wrong and call chip_ready right after the block erase command has been issued. The modified chip_ready does a busy wait polling DQ 10000000 times. If DQ change from last poll, the new value and the poll number is stored. At the end of the busy wait, the stored data is printed out. This is a typical printout (i is poll number and "data" is DQ):

i = 0, read: 0000FF5F
i = 1, read: 0000FF1B
i = 2, read: 0000FF5F
i = 3295, read: 0000FF1B
i = 8782, read: 0000FF5F
i = 14332, read: 0000FF1B
i = 19884, read: 0000FF5F
i = 25168, read: 0000FF1B
i = 25170, read: 0000FF5F
i = 25431, read: 0000FF1B
i = 30968, read: 0000FF5F
i = 42071, read: 0000FF1B
i = 47623, read: 0000FF5F
i = 65067, read: 0000FF1B
i = 105299, read: 0000FFFF
i = 9999999, read: 0000FFFF

So contrary to what is documented in the SST data sheet and also to what appear to be the normal operation of an AMD compatible flash, the toggle bits only toggle on consecutive reads a few times and then toggle far less frequently. Does anyone know what is going on ? Is this a faulty chip ? Any help would be appreciated.

Best regards,

Niels Gram