Request for testing: AMD/Fujitsu flash chips

[Mike Rapoport]

David Woodhouse wrote:
> For a long time, there's been confusion about the "unlock addresses" for
> AMD-compatible NOR flash -- the chip definition in our table have an
> _array_ giving the addresses at which we should do the magic unlock
> write cycles, according to the different modes (16-bit, 8-bit) that the
> chip could be used in.
> 
> For a while now, we've been deliberately ignoring all but the first
> entry in that array, on the basis that it shouldn't actually vary -- the
> chip needs the same levels on the same address lines, whatever mode it's
> in. The data sheets can be very confusing... for example:
> 
> 	5. The system should generate the following address patterns:
> 	    Word Mode: 555H or 2AAH to addresses A0 to A10
> 	    Byte Mode: AAAH or 555H to addresses A-1 to A10
> 
> I've just got rid of the array of unlock addresses, and _attempted_ to
> make the code cope and work again. I would very much appreciate some
> testing, before I put that in the MTD git tree:
> 
> 	git://git.infradead.org/~dwmw2/jedec-unlock.git
> 	http://git.infradead.org/?p=users/dwmw2/jedec-unlock.git

I've tested with Eon EN29SL800 (not in the main tree). Works Ok.


-- 
Sincerely yours,
Mike.