cfi_cmdset_0001: Use max value for block erase timeout?
nico at cam.org
Fri Aug 17 22:55:02 EDT 2007
On Fri, 17 Aug 2007, Anders Grafström wrote:
> I am experiencing a problem with a failing erase block on
> Intel J3 Strataflash. After receiving the block erase command,
> the chip returns to ready state after 25 seconds (see errata #2).
> The status register says 0xA0.
> The MTD block erase timeout is set to the typical value which is 1 second.
> So the 1 second timeout happens. JFFS2 puts the block on the bad_list and
> continues, but all operations on the chip within the next 24 seconds will fail
> since get_chip() will timeout. JFFS2 is not happy.
> Increasing the block erase timeout to 32 seconds solves the problem for me.
> A couple of warnings about the failed block erase is printed but JFFS2 has
> no errors.
> This brings the question of which timeout value should be used for block erase
> (and word write and buffer write), typical or max?
Ideally, the typical value should be used for the command wait delay.
The max value should be the hard limit after which a timeout error is
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