NAND driver question

[Ramesh, Subramanian (HPSL-Firmware)]

	I don't know if this is the right forum, but I have a question.
What we have is a powerpc board running 2.6.11 kernel (curently using a
NOR flash) and the HW guys are proposing putting a ST micro 512MB NAND
on the board, but behind an FPGA. They are also proposing to have a
separate chip select for the NAND's address range so that the accesses
to that range will be a straight "pass through" for the FPGA. My concern
is that what impact will this have on the driver. Ideally, it should
work as is, but I am not sure. Any pointers? 

Thanks.
--Ramesh