[PATCH] AT91RM9200 NAND support

[Thomas Gleixner]

On Tue, 2006-06-20 at 15:01 +0200, Savin Zlobec wrote:
> Chip not ready in nand_command():
> Last caller: c012afa8 (nand_base.c:736)
> Last command: 0x70
> Current caller: c012bf8c (nand_base.c:1374)
> Current command: 0x80
> 
> 716     static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip, int state)
> ...
> 733             if ((state == FL_ERASING) && (chip->options & NAND_IS_AND))
> 734                     chip->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1);
> 735             else
> 736                     chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
> 
> 1367    static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
> 1368                               const uint8_t *buf, int page, int cached)
> 1369    {
> 1370            int status;
> 1371
> 1372            chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
> 1373
> 1374            chip->ecc.write_page(mtd, chip, buf);
> 
> Chip not ready in nand_command():
> Last caller: c012afa8 (nand_base.c:736)
> Last command: 0x70
> Current caller: c012b644 (nand_base.c:988)
> Current command: 0x00
> 
> 953     static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
> ...
> 987                             if (likely(sndcmd)) {
> 988                                     chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
> 989                                     sndcmd = 0;
> 990                             }

This gets even more mysterious. I both cases the previous function was
nand_wait(), which blocks in the wait function until ready state is
reached. 

I really have no clue, how the chip gets into busy state between the
return from nand_wait() and the next commmand. 

Is there anything playing with the enable pin of the nand chip between
those commands ? Those chips have an autoread feature on power on. Is
the power switched off ?

Have you any other modifications to at91_nand.c I'm not aware of ?

	tglx