[Yaffs] bit error rates --> a vendor speaks

[Artem B. Bityutskiy]

Josh Boyer wrote:
> Often times the eraseregions have no practical use for the software
> involved.  Take the Intel P30 for example.  It has a few eraseblocks
> at either the top or bottom of the chip that are different eraseblock
> size.  
This explains why putting this all together in one mtd-> structure is 
bad  (they have different eraseblocks size).

> If you have different eraseregions show up as different MTD devices
> (or partitions which are essentially the same thing in this
> discussion),
Err, actually partitions are better, because they are handeled by the 
same flash driver.

> then you have to manually concatenate them back into a
> single device.
What for do you need to concatenate them back? Different erase regions 
are used for completely different purposes, right? So if you work with 
the small "boot" region, you don't normally need the rest of the flash 
and vice versa.

My point is that there should be a generalized flash model like this:

1. there are only 3 operations: read, write, erase;
2. erase is done in terms of eraseblocks, eraseblocks are all equivalent 
in size;
4. there is a minimal input/output unit exists;

That's all. Erase regions and OOB is out of this simple flash model, do 
you see what I mean? Add your erase regions to this model and you'll end 
up with a mess. Organize these regions as different instances of the 
above generalized model, and you have a very nice picture.

-- 
Best Regards,
Artem B. Bityutskiy,
St.-Petersburg, Russia.