[PATCH/RFC] CFI XIP support on chip with RWW

[Nicolas Pitre]

On Thu, 21 Dec 2006, Alexey Korolev wrote:

> Hi
> 
> The XIP awareness feature in MTD provides a safe way to use XIP but it
> introduces some significant issues too,
> The issues are following:
> 
> 1.	Large interrupt latency
> 2.	Lower write/erase performance (due to suspend/resume) 3.	~100%
> CPU load during write or erase operations with flash
> 
> In other hands if chip with Read While Write feature (or several chips) are
> used it is possible to avoid all these XIP related issues.

Yep.

> To provide it from s/w it is necessary to separate wait procedures for RWW
> partitions with XIP and without XIP. Idea is simple user specify memory region
> planned for XIP - according to this data, the code marks XIP flag for some RWW
> partitions. RWW partitions with XIP flag are handled by wait procedures with
> XIP awareness. All other RWW partitions are handled by default wait
> procedures. Please see the code below. Your comments are welcom

There are small coding style issues, like "if ( foo )" instead of
"if (foo)", please see Documentation/CodingStyle).

Also wouldn't it be better to identify the XIP-able area(s) with new MTD 
partition flags instead?


Nicolas