[PATCH/RFC] MTD: Striping layer core

[Thomas Gleixner]

On Mon, 2006-04-03 at 10:14 +0400, Vitaly Wool wrote:
> Given that some modern NAND controllers have the ability to generate 
> interrupt when they're done, I would think about complete redesign of 
> the MTD NAND layer. I'd like to see the fully asynchronous base model 
> here (i. e. mtd->send_write_cmd/send_read_cmd or something similar) and 
> synchronous interface on top of that, just like, say, the current SPI 
> core works.
> This would allow to be more flexible in waiting for completion and also 
> would IMO make striping implementation for NAND more straightforward. 
> Does that make sense?

In general yes, but it does not solve the problem, where you have _ONE_
shared line for ready/busy -> interrupt for all chips connected to the
hardware controller, nor does it solve the general serialization
requirements to access the controller.

	tglx