[patch] cfi: remove warning message on expected behaivor

[David Vrabel]

Jan Pedersen wrote:
> When an erase operation is in progress, the DQ5 (data bit 5 / exceeded
> timing limit) pin on the flash chips may raise just before operation
> complete is detected. This is expected behaivor because when the erase is
> complete, DQ5 switches from 'exceeded timing limit' to 'data bit 5' which
> therefore might be read as '1' just before operation complete is detected.
> This fix is well tested.

If you look at the current cfi_cmdset_0002.c (in 2.6) you'll notice that
all it does it check for toggling bits.  The software timeout handles
failed erases and writes rather than checking DQ5.

Trying to handle the various error bits was deemed too tricky/complex to
get right for interleaved chips.

David Vrabel
-- 
David Vrabel, Design Engineer

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