JFFS3 & performance

[Artem B. Bityuckiy]

On Fri, 7 Jan 2005 jasmine at linuxgrrls.org wrote:

> 
> 
> On Fri, 7 Jan 2005, Artem B. Bityuckiy wrote:
> 
> > Hmm, why is this better? (I suppose you mean cache line size)
> 
> Because ARM926 has a compulsory cache penalty cycle on every line
> traversal.  (This is why ARM926 is about 8% slower than ARM925 at
> the same clock frequency.)  There is also a penalty on every eighth
> page mapped in, because there are only eight microTLB entries and
> there are wait states on the main TLB.
> 
> > But bake them word-aligned is good.
> 
> Not word-aligned, cacheline-aligned.
> 
> -J.
> 
But the reason why I include that loops is dictated by our discussions 
about backward/forward CRC calculations and CPU cache benefits. CRC's are 
calculated reading bytes. So I don't think we should take into account 
cache line size in our particular case.

--
Best Regards,
Artem B. Bityuckiy,
St.-Petersburg, Russia.