JFFS3 & performance

Artem B. Bityuckiy dedekind at infradead.org
Fri Jan 7 09:50:56 EST 2005


On Fri, 7 Jan 2005 jasmine at linuxgrrls.org wrote:

> 
> 
> On Fri, 7 Jan 2005, Artem B. Bityuckiy wrote:
> 
> > Hmm, why is this better? (I suppose you mean cache line size)
> 
> Because ARM926 has a compulsory cache penalty cycle on every line
> traversal.  (This is why ARM926 is about 8% slower than ARM925 at
> the same clock frequency.)  There is also a penalty on every eighth
> page mapped in, because there are only eight microTLB entries and
> there are wait states on the main TLB.
> 
> > But bake them word-aligned is good.
> 
> Not word-aligned, cacheline-aligned.
> 
> -J.
> 
And it seems difficult to take into account a lot of platform-dependent 
things. Isn't it better to have one universal test?

--
Best Regards,
Artem B. Bityuckiy,
St.-Petersburg, Russia.




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