Regarding NAND MTD Driver Help Required

[Moreshwar Salpekar]

Dear All,
I am new to this list. I have just gone through the latest code and
documentation of NAND Flash MTD Driver. I am facing certain problems in
understanding this code as I need to modify this code for my board. I would
like somebody to help me understand this code. The problems are as follows:
1. The code on this site and documentation is different from source code of
mtd in drivers/mtd/nand even in kernel version 2.6.7. The following files
are specifically different:
The code in Linux source includes nand.c here I think it is nand_base.c,
there is no file nand_ids.c in Linux source.

2. Which version of kernel is this code applicable to ?

3. What is the latest stable version of this code? What about snapshots in
this code

4. What are the bus widths of NAND flash supported (code in kernel supports
8-bit but your version lists a constant BUSWIDTH_16 which I think implies
that 16-bit bus width is supported)? I need to support 8 and 16 bit right
now. What are the bus other options that may be set in the nand_flash_dev
structure

5. Does the code support GPIO mode of addressing or Address lines? The code
uses register to control ALE, CLE and nCE signals and uses another register
(IO_ADDR) to driver date lines. I think this implies that GPIO or some other
IO pins are being used to drive ALE, CLE and nCE rather than
microprocessor/microcontroller driving these signals. I think that this
could slower down the operation of NAND Flash if software drives the
operation.

6. What is SPIA board as mentioned in codes? I want to check how is the NAND
flash connected to microprocessor/ microcontroller as I may need to modify
the code to suit my requirements (addressing mode).

7. If anybody has whole code that is based on addressing lines please give
me the same.

Thanks in advance
Regards
Moreshwar Salpekar