Different nand interface

[Joshua Wise]

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> I need some advice on how to support a board that has a hardware state
> machine
> that creates a parallel bus style interface to the NAND chip.  It is
> totally
> different from the standard 8 IO signal controls. 

I'm not certain if this is what you're looking for, but the iPAQ h1910 has 
NAND connected to the address pins. (Is this what you mean?) Take a look at 
the NAND code in handhelds.org CVS (module linux/kernel26, I think, although 
if h1910 flash is not an option there, try module linux/kernel) - it's just 
standard MTD NAND, except with some changes not to do moronic caching of 
IO_ADDR_R and IO_ADDR_W. (You can also look at the 1910 flash driver to see 
how I change IO_ADDR_R/W based on ALE and CLE.)

/j

- -- 
Joshua Wise | www.joshuawise.com
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Quote       | <lilo> I akilled *@* by mistake
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