Nand Flash with 2048 Byte Page sizes

[Greg A. Martin]

Thanks for suggestion (and volunteering?) to get guidance. I am in the
early stages of porting u-boot with nand support to a PowerPC 405GP
system. I am currently just trying to make sure the hardware is designed
properly.  Any suggestions are welcome. My biggest concern now (and
ignorance) is how to allocate the spare bytes for the additional ecc
required
for the larger page size. Another question I have is the current structures
(nand_chip and/or nand_flash_dev) don't seem to have enough information
about
the number of column address bytes and page address bytes that need to be
sent
to the device.


-----Original Message-----
From: Charles Manning [mailto:manningc2 at actrix.gen.nz]
Sent: Thursday, October 09, 2003 12:47 PM
To: gregmartin at lucent.com
Cc: linux-mtd at lists.infradead.org
Subject: Re: Nand Flash with 2048 Byte Page sizes


On Friday 10 October 2003 03:04, David Woodhouse wrote:
> On Thu, 2003-10-09 at 08:50 -0500, Greg A. Martin wrote:
> > Hi,
> > I haven't seen any references yet to the newer NAND devices from
> > Samsung that have 2048 byte pages with 64 bytes extra data. The Part
> > numbers are K9F1G08U0M and K92G08U0M. These are 1 and 2 Gbit devices
> > with 11 bit column addresses and 16 or 17 bit page addresses that need
> > two byte read commands. Any idea if support for these devices will be
> > forth coming soon, or do I get to blaze a trail?
>
> You get to blaze a trail. :)

I'd like to suggest that when you go blaze that trail you ask guidance
before
and you go. There are many possible direction, but certain of these are more
useful to the file systems that get to use the code.

-- Charles