Handling multiple NAND chips

[J.D. Bakker]

At 12:27 +1200 26-07-2003, Charles Manning wrote:
>One thing to watch out for: some NAND chips have very high pin capacitance
>and a fan-out of 8 might get a bit freaky.

The Toshiba TH58100s I'm using have 20pf pin capacitance. On a fully 
populated board (8 chips) this increases the access time by 5-10ns. 
I'm not too worried about this -- the main purpose for this design is 
solid state data recording, which is already limited by program/erase 
time.

Thanks for reminding me, though; I need to increase the processor's 
access time to these memory regions.

>You'll need quite a bit of RAM for holding various data structures. :-).

I have 160MB, will that do for a 1GB yaffs mount ?

By the way, does yaffs have inherent limitations wrt file system size 
I should worry about ?

JDB
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