Handling multiple NAND chips

[David Woodhouse]

On Fri, 2003-07-25 at 11:12, J.D. Bakker wrote:
> Hi all,
> 
> I have an expansion board for the LART (an embedded computer based on 
> the DEC/Intel StrongARM) with eight NAND flash devices on it. As 
> suggested by the Toshiba datasheet, they share data, CLE, ALE, nWE 
> and nRE and RDY. Each chip has its own nCE line.

Btw, I suspect that when we come to implement this, we'll find you'd get
much more parallelism if you had _separate_ FR/B# lines for each chip. 

If you can hook your FR/B# lines up to an IRQ-capable GPIO, that'd be
cute too.

-- 
dwmw2