Fw: corrupt my NAND flash device
dwmw2 at infradead.org
Thu Jul 3 21:43:21 EDT 2003
On Wed, 2003-07-02 at 18:53, Jasmine Strong wrote:
> The timings for the 405 EBIU bus do not match the required timings for
> the Toshiba chip's read cycle. There is no good solution to this
> We ended up putting the !RE pin onto a GPIO, but this caused (huge)
> problems with interrupts and so forth.
Hmmm. Perhaps this is a situation in which using something like a
DiskOnChip might be useful. The DiskOnChip ASIC isolates the flash bus
from the host and gives you a sensible pipeline for data transfer;
dual-host-cycle read/write accesses when appropriate.
Otherwise yes, you need to invent the same kind of thing to meet the
timing constraints of the NAND chip.
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