optimum geometry

Adam Wozniak adam.wozniak at comdev.cc
Fri Jan 18 14:55:06 EST 2002

I've got 8 x 8 bit chips forming my 64 bit wide flash area.
An erase block on a single chip is 128K bytes, so I've really
got 128K * 8 == 1024 K == 1 M erase blocks.  My JFFS2 partition
is 96 Megs, so I've only got 96 erase blocks.

I'm beginning to fear that this is far from optimum.  What is an
optimum erase block size?

I could drop back and rewrite the MTD driver to address each
chip seperately, but I'm concerned that would be both messy and
tough on performance.


Adam Wozniak (KG6GZR)   COM DEV Wireless - Digital and Software Systems
awozniak at comdev.cc      3450 Broad St. 107, San Luis Obispo, CA 93401
                        Voice: (805) 544-1089       Fax: (805) 544-2055

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