Support for parallel access in nand chips

David Woodhouse dwmw2 at infradead.org
Mon Feb 25 20:25:09 EST 2002


rcorlan at pcnet.ro said:
>  ok - i was going to make a separate source anyway. Do you know if the
> upper layers mind the 32k erase size?

They'll be fine - it's still smaller than the typical erase size on NOR 
flash.

If you want to run JFFS2 on it, the ECC layout needs to be decided.

--
dwmw2






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