mtd_info_t.erasesize

[Kári Davíðsson]

> -----Original Message-----
> From: Alice Hennessy [mailto:ahennessy at mvista.com]
> Sent: 22. mars 2001 00:56
> To: Kári Davíðsson
> Cc: mtd at infradead.org; ahennessy at mvista.com
> Subject: Re: mtd_info_t.erasesize
> 
> Well,
> 
> I think you are the first one to use an Intel CFI chip that 
> has different
> erasesizes.

o.k.

> The logic to handle different erase sizes is in the 

Yes but I do not totally agree with that logic. It assumes that
the erasesize is the size of the biggest sector in the flashdevice.

I can only see two ways around that, either make the application aware
of
the diffrent erase_size region through the mtd_info_t structure or
make the ioctl(fd, MEMERASE,...) return where the last erase call ended,
e.g.

while(0 != einfo.length){
	int erased;
	ioctl(fd, MEMERASE, &einfo, &erased);
	einfo.start+=erased;
	einfo.length-=erased;
}

> cfi_cmdset_0002.c file
> which handles
> the AMD chips but not in the cfi_cmdset_0001.c for Intel chips as yet.
> Does the Intel chip give the correct order of the erase regions in the
> query to match the order in the flash?  Special
> code had to be added for the AMD chips to figure out the 
> correct order of
> the erase regions on the chip.

Well it seems to export the erase regions correctly. I have a small
patch that
I wan't to test better before I post it here to the cfi_cmdset_0001.c
that identifies
the erase regions correctly.

> 
> Alice

K.D.


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