Oh, the many joys of MTD...

[Kevin Jacobs]

On Thu, 8 Mar 2001, Nicolas Pitre wrote:
> > My first questions is likely something fairly basic.  I've read over much of
> > the MTD source and it seems that many of the erase and write functions do
> > not deal with concurrent access and CPU cache issues.  What happens when a
> > {read,write,erase} request comes in for a sector that is being
> > {written,erased}?
> 
> Those are exclusively protected by state machines and locks.  For example,
> see the usage of chip->state in cfi_cmdset_0001.c.

Only cfi_cmdset_* does this.  jedec, amd_flash, etc. do not.

> 
> > Also, is it assumed that the memory mapped for MTD devices will not be
> > cached by the CPU?  If so, is it feasible to add support.  If not, where is
> > code to flush/update the cache after a write or erase operation?
> 
> The device mapping is done with the ioremap() call which is responsible for
> providing a non-cacheable mapping.

Then what does ioremap_nocache do?

-Kevin



--
Kevin Jacobs
The OPAL Group - Enterprise Systems Architect
Voice: (216) 986-0710 x 19         E-mail: jacobs at theopalgroup.com
Fax:   (216) 986-0714              WWW:    http://www.theopalgroup.com




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