Oh, the many joys of MTD...

[Kevin Jacobs]

On Thu, 8 Mar 2001, David Woodhouse wrote:
> jacobs at penguin.theopalgroup.com said:
> >  My first questions is likely something fairly basic.  I've read over
> > much of the MTD source and it seems that many of the erase and write
> > functions do not deal with concurrent access and CPU cache issues.
> > What happens when a {read,write,erase} request comes in for a sector
> > that is being {written,erased}?
> 
> See the state machine in cfi_cmdset_000[12].c. We wait until the operation 
> which is currently in progress has completed. Theoretical support for 
> interruption of erases and writes is there, but it's not yet implemented.

That seems to be a feature of the cfi_cmdset_* but not of jedec.c,
amd_flash.c, among others.


> > Also, is it assumed that the memory mapped for MTD devices will not be
> > cached by the CPU?  If so, is it feasible to add support.  If not,
> > where is code to flush/update the cache after a write or erase
> > operation? 
> 
> It's assumed that it won't be cached, you are correct. 

If a flash device was cached then writes should be fine, correct?  Erase
operations would require Writing 0xFF to erased sectors should make the
cache coherent, right?

-Kevin

--
Kevin Jacobs
The OPAL Group - Enterprise Systems Architect
Voice: (216) 986-0710 x 19         E-mail: jacobs at the
Fax:   (216) 986-0714              WWW:    http://www.theopalgroup.com




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