Supported flash memory

[Nicolas Pitre]

On Fri, 5 Jan 2001, David Woodhouse wrote:

> Russ.Dill at asu.edu said:
> >  I've noticed LART connects address and data lines to flash in
> > positions most convienent to route. Does this break any CFI
> > functionality?
>
> What do you mean? It's generally considered quite rude for hardware
> designers to connect nets to _completely_ random places on the chips,
> although sometimes it wouldn't really surprise me.

They did!  My recommendation to Erik Mouw (the software guy from the LART
team) was to modify cfi_build_cmd() to sweezle the bits appropriately.


Nicolas



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